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[Windows Develop] fifo源程序

Description: fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
Platform: | Size: 1136 | Author: 许 | Hits:

[VHDL-FPGA-Verilog] fifo_VHDL

Description: FIFO的源代码，详细描述FIFO的工作原理和过程，用VHDL编写。-FIFO of the source code, a detailed description of the work of FIFO principle and process of preparation with VHDL.
Platform: | Size: 9216 | Author: 胡志敏 | Hits:

[VHDL-FPGA-Verilog] fifo8_8

Description:
Platform: | Size: 1024 | Author: 李松 | Hits:

[Software Engineering] Asyn_FIFO_Design

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 228352 | Author: 刘强 | Hits:

[Software Engineering] multiplier_8bit

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 46080 | Author: 刘强 | Hits:

[Windows Develop] sdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[OS Develop] asyn_fifo

Description: verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
Platform: | Size: 2048 | Author: nihao | Hits:

[VHDL-FPGA-Verilog] fifoi

Description: 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
Platform: | Size: 2048 | Author: 云 | Hits:

[VHDL-FPGA-Verilog] gencontrol

Description: 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
Platform: | Size: 1024 | Author: ted yang | Hits:

[VHDL-FPGA-Verilog] SYNC_FIFO

Description: its simple fifo.which is used to first in first out for vhdl source code
Platform: | Size: 1024 | Author: Viral | Hits:

[VHDL-FPGA-Verilog] caiyang

Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
Platform: | Size: 338944 | Author: 于银 | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

[VHDL-FPGA-Verilog] simpleFIFO

Description: FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware description language source code
Platform: | Size: 137216 | Author: 陳皇仁 | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[VHDL-FPGA-Verilog] vhdlfifo1

Description: fifo - source code for first in first out(fifo) using VHDL
Platform: | Size: 1223680 | Author: nagarjuna reddy | Hits:

[VHDL-FPGA-Verilog] vhdlfifo

Description: fifo- source code for fifo using VHDL
Platform: | Size: 1223680 | Author: nagarjuna reddy | Hits:

[VHDL-FPGA-Verilog] aFifo

Description: it is a vhdl source code for FIFO
Platform: | Size: 2048 | Author: Hadi | Hits:

[VHDL-FPGA-Verilog] EDA-experiments-based-on-VHDL

Description: 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
Platform: | Size: 4096 | Author: shi xin | Hits:

[source in ebook] FIFO

Description: FPGA内部FIFO存储器设计的vHdl源代码-FPGA internal FIFO memory design vHdl source code
Platform: | Size: 1024 | Author: 罗智勇 | Hits:

[VHDL-FPGA-Verilog] syn_fifo

Description: 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
Platform: | Size: 1024 | Author: 王敏志 | Hits:
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